1. Field of the Invention
This invention relates to a semiconductor device for creating a voltage-down (and/or booster) potential by using an internal voltage-down (and/or booster) converter with respect to an external power supply and applying the potential as an internal power supply voltage to a chip internal circuit, and more particularly to a semiconductor device capable of suppressing the current peak flowing into or from the external power supply.
2. Description of the Related Art
With the development of the fine patterning technique of semiconductor, chips such as large-scale and high-speed 32 bit- or 64 bit-MPUs containing several millions of transistors and large-capacity 16 Mbit-DRAM, 64 Mbit-DRAMs or the like are mass-produced. Therefore, the number of transistors used rapidly increases and a current consumed in the chip is extremely increased even though the power supply voltage Vcc is lowered from 5 V to 3.3 V or 3 V. An increase in the current consumption causes a serious problem of generation of power supply noise.
Particularly, if chips having a large peak current are operated at the same time, the power supply is required to have a large current supplying ability and it is necessary to dispose a large number of capacitors for stabilizing the power supply voltage on a PCB (Printed Circuit Board). Therefore, a large area for formation of capacitors is required.
Recently, in order to reduce the current consumption (power consumption) and enhance the reliability of the device, various methods for creating an internal voltage-down potential (V.sub.int) which is lower than the power supply voltage (V.sub.cc) in the chip by use of a DRAM or CPU and applying the internal voltage-down potential to the chip internal circuit have been proposed. One example of a chip containing a conventional voltage-down circuit is shown in FIG. 1. A voltage-down circuit 2 for lowering V.sub.cc to V.sub.int by use of a transistor Q and an operational amplifier OP is connected in series with an internal circuit 1.
Generally, when the voltage-down circuit is not used, the power P is set to P=CV.sup.2 f if the power supply voltage is V.sub.cc, the chip charging/discharging capacitance is C, and the clock frequency is f. If the internal power supply voltage is set to V.sub.int (&lt;V.sub.cc) when the voltage-down circuit is used, the power is set to P=(V.sub.int /V.sub.cc)CV.sup.2 f and is reduced even if the external power supply voltage is kept at V.sub.cc.
However, in order to keep V.sub.int at a constant voltage, it is necessary to supply a current having the same waveform as that of a current (I.sub.ss) flowing in the internal circuit 1 to the voltage-down circuit 2 in the circuit of FIG. 1. That is, the current flowing in the transistor Q is set equal to I.sub.ss. Thus, it is necessary to set the relation of I.sub.cc (t)=I.sub.ss (t), and in this case, V.sub.int can be kept constant.
In the circuit of FIG. 1, V.sub.int and a reference voltage V.sub.ref1 are used as the inputs to the operational amplifier and the output thereof is supplied to the gate of Q. In this case, if V.sub.ref1 &gt;V.sub.int, Q is turned "ON", and if V.sub.ref1.ltoreq.V.sub.int, Q is turned "OFF", and as a result, the internal voltage V.sub.int is kept at the same value as the potential of V.sub.ref1.
In the above circuit, as shown in FIG. 2, a variation in the voltage is reduced in comparison with a case wherein the circuit is directly connected to the external power supply V.sub.cc when I.sub.cc =I.sub.ss, but a current supplied from the external power supply V.sub.cc flows so as to become equal to the current peak (I.sub.cc) caused by the operation of the internal circuit (I.sub.ss =I.sub.cc), and as a result, V.sub.cc, V.sub.ss vary and the noise influence is large. Further, when taking not only the internal portion of the chip but also the package and PCB into consideration, variations in V.sub.cc, V.sub.ss become larger and cause a serious problem since inductances occur in various portions as shown in FIG. 3. For example, in FIG. 3, if the chip A has a large current peak, not only the chip A but also the chip B is influenced.
Further, the influence by the inductance is also exerted on the internal voltage-down potential V.sub.int of its own chip which should be kept at a constant potential. That is, a variation in consumption current causes a further variation in the power supply voltage by the parasitic inductances of inner leads and bonding wires on the PCB. A variation of higher frequency component than the response characteristic of the internal voltage-down circuit exists, thereby fluctuation in the high-frequency component of a variation in the external power supply voltage V.sub.cc is transmitted as fluctuation in the internal voltage-down potential, and thus the internal power supply voltage V.sub.int varies by the influence of the external inductance.
As described above, in the conventional chip and conventional voltage-down circuit, a large fluctuation in the power supply voltage occurs and this becomes larger as the integration density becomes higher. As a result, the power supply noise becomes larger, and in order to cope with this problem, it is necessary to use a main power supply having a larger supply ability and a larger number of stabilizing capacitors. Further, various problems such as deterioration in the operation speed and V.sub.cc margin occur due to the presence of noise occur. The above conventional circuit design is made for each chip so as to stabilize only the operation of the chip against the external noise and self noise.